SR Latch
Definition of Latch
A latch is a basic memory element used in digital electronics to store one bit of information. Unlike combinational circuits, a latch can remember its previous output state even after the input is removed.
Types of Latch
- SR Latch
- D Latch
SR Latch using NOR Gate
An SR latch using NOR gates is formed by connecting two NOR gates in a cross-coupled manner. It has two inputs: Set (S) and Reset (R).
Diagram of S-R Latch using NOR Gate
Operation of SR Latch
- \( S = 1 \) sets the output (\( Q = 1 \))
- \( R = 1 \) resets the output (\( Q = 0 \))
- \( S = 0,\; R = 0 \) → No change (memory state)
- \( S = 1,\; R = 1 \) → Invalid condition
Truth Table of SR Latch (NOR)
| \( S \) | \( R \) | \( Q_{next} \) | \( \mathrm{Operation} \) |
|---|---|---|---|
| \(0\) | \(0\) | \(Q\) | \(\mathrm{Hold}\) |
| \(0\) | \(1\) | \(0\) | \(\mathrm{Reset}\) |
| \(1\) | \(0\) | \(1\) | \(\mathrm{Set}\) |
| \(1\) | \(1\) | \(\mathrm{Invalid}\) | \(\mathrm{Invalid}\) |
SR Latch using NAND Gate
An SR latch using NAND gates is constructed by cross-coupling two NAND gates. In this configuration, the external inputs are S (Set) and R (Reset), but due to the NAND gate operation, they behave as active LOW internally.
Internally, the effective inputs to the NAND latch are:
- \( \overline{S} = \text{NOT}(S) \)
- \( \overline{R} = \text{NOT}(R) \)
This means the latch responds when S = 0 or R = 0.
Diagram of SR NAND Latch
Operation of SR NAND Latch
- Set Condition: \( S = 0,\; R = 1 \Rightarrow Q = 1,\; \overline{Q} = 0 \)
- Reset Condition: \( S = 1,\; R = 0 \Rightarrow Q = 0,\; \overline{Q} = 1 \)
- Hold (Memory) Condition: \( S = 1,\; R = 1 \Rightarrow Q_{next} = Q_{previous} \)
- Invalid Condition: \( S = 0,\; R = 0 \Rightarrow Q = 1,\; \overline{Q} = 1 \) (Violation of complement property)
Truth Table of SR Latch using NAND Gate
| \( S \) | \( R \) | \( Q_{next} \) | \( \mathrm{Operation} \) |
|---|---|---|---|
| \(1\) | \(1\) | \(Q\) | \(\mathrm{Hold}\) |
| \(0\) | \(1\) | \(1\) | \(\mathrm{Set}\) |
| \(1\) | \(0\) | \(0\) | \(\mathrm{Reset}\) |
| \(0\) | \(0\) | \(1\) | \(\mathrm{Invalid}\) |
Important Notes
- NAND-based SR latch uses active LOW logic internally
- Condition \( Q = \overline{Q} = 1 \) is not allowed
- Widely used due to faster NAND gate implementation
SR Gated Latch
An SR gated latch is an improved version of the SR latch that uses an Enable (E) or Clock input. The latch responds to inputs only when the enable signal is active.
Diagram of SR Gated Latch
Working Principle
- When \( E = 0 \) → Output remains unchanged (latch is disabled)
- When \( E = 1 \) → Latch responds to \( S \) and \( R \) inputs (latch is enabled)
Advantage
- Prevents accidental state changes
- Controlled operation
- Used in synchronous circuits
D Latch
A D latch (Data latch) is derived from the SR latch. It eliminates the invalid condition by ensuring that S and R are never HIGH at the same time.
Diagram of D Latch
Working
- Single input: \( D \) (Data)
- When \( E = 1 \), output follows the input (\( Q = D \))
- When \( E = 0 \), output is stored (memory state)
Truth Table of D Latch
| \( D \) | \( E \) | \( Q_{next} \) |
|---|---|---|
| \(0\) | \(1\) | \(0\) |
| \(1\) | \(1\) | \(1\) |
| \(X\) | \(0\) | \(Q\) |
Advantages of D Latch
- No invalid state
- Simple and reliable
- Used in registers and memory units